This paper presents a new circular buffer architecture for FIR/IIR filter hardware implementations. Different from traditional circular buffer architecture, the new architecture does not need read pointers for circular input/output state buffers. Instead, it keeps the state addresses linear, and uses an address mapping algorithm to calculate coefficient addresses. By keeping the state addresses linear, design is simplified. With removal of circular read pointers, the number of flip-flops is reduced and so is the power. The new architecture is dual to the traditional circular buffer architecture. It achieves equivalent performances with less design complexity, less logic gate count, and less power.