In this paper, a truly divider-less, robust and highly configurable lock assist and automatic frequency calibration (AFC) for sub-sampling phase-locked loops (SSPLL) is demonstrated. The design uses a secondary, low-frequency ring-oscillator charge-pump PLL and exploits shifted-phase sub-sampling to obtain frequency information. A fractional ratio between the reference clock of the 56 GHz SSPLL and the sample clock of the AFC is leveraged to achieve sub-harmonic and arbitrary slow frequency detection. Apart from the analog front-end with a high-speed track-and-hold and a simple low-speed, low-resolution analog-to-digital converter, the entire lock detection, frequency processing and calibration is implemented as digital logic.