Digital hardware implementations of Spiking Neural Networks designed using Selective Input Sparsity (SIS) are proposed for edge inference applications in image classification where the image acquisition environment is controlled. These sparsely connected networks are well-suited to area-constrained applications as they require fewer neurons and synapses than baseline Fully Connected (FC) networks of analogous structures. The SIS networks were validated on FPGA, and baseline FC networks were also implemented on FGPA for comparison. The SIS networks require fewer hardware resources and make inferences faster than the baseline FC networks without substantial impact on the classification accuracy.