A time-interleaved analog-to-digital converter (TI-ADC) with voltage controlled oscillators (VCOs) can efficiently convert radio-frequency (RF), a few gigahertz, signals into digital ones with medium resolution. This ADC, however, suffers from aliasing signals, and harmonic distortion (HD) and intermodulation (IM) products owing to the channel mismatches and the nonlinearity of the VCO gain, respectively. We first present a digital background correction to reduce the mismatch aliasing signals and the third-order HD and IM products of four-channel TI-ADCs with VCOs. Our method utilizes the complex and decimated signals, sent from a direct-RF receiver, and adaptive filters with cross-correlation functions of these signals. Then, we implement the correction circuit with 24-bit floating point arithmetic to compromise between the accuracy and power consumption. Simulations show that the correction improves the two-tone spurious-free dynamic range (SFDR) of a TI-ADC with a sampling frequency of 3,680 MHz from 54.8 dB to 66.7 dB and the circuit designed with a 65-nm CMOS technology operates at 4.3 mW and a rate of 57.5 MS/s.