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Video s3
    Details
    Presenter(s)
    Koji Inoue Headshot
    Display Name
    Koji Inoue
    Affiliation
    Affiliation
    Kyushu University
    Country
    Author(s)
    Display Name
    Iori Ishikawa
    Affiliation
    Affiliation
    Kyushu University
    Display Name
    Ikki Nagaoka
    Affiliation
    Affiliation
    Nagoya University
    Display Name
    Ryota Kashima
    Affiliation
    Affiliation
    Nagoya University
    Display Name
    Koki Ishida
    Affiliation
    Affiliation
    Kyushu University
    Display Name
    Kosuke Fukumitsu
    Affiliation
    Affiliation
    Kyushu University
    Display Name
    Keitaro Oka
    Affiliation
    Affiliation
    Kyushu University
    Display Name
    Masamitsu Tanaka
    Affiliation
    Affiliation
    Nagoya University
    Display Name
    Satoshi Kawakami
    Affiliation
    Affiliation
    Kyushu University
    Display Name
    Teruo Tanimoto
    Affiliation
    Affiliation
    Kyushu University
    Display Name
    Takatsugu Ono
    Affiliation
    Affiliation
    Kyushu University
    Display Name
    Akira Fujimaki
    Affiliation
    Affiliation
    Nagoya University
    Display Name
    Koji Inoue
    Affiliation
    Affiliation
    Kyushu University
    Abstract

    This paper presents a design of ultra-high-speed, low-power arithmetic unit that supports variable bit-width operations with the single flux quantum (SFQ) technology. Because of the high-speed nature of superconductor devices, we can achieve extremely high power-performance efficiency that cannot be achieved by state-of-the-art CMOS devices. To implement the complex function to support the variable bit-width feature, we introduce a novel circuit architecture to maintain the high-speed operation over 50GHz. Our prototype chip design successfully demonstrate 53.5GHz 1.59mW operations.

    Slides
    • Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device (application/pdf)