NVM based accelerators for Machine Learning (ML) have become widely popular as they offer high energy efficiency and lower latency due to parallel matrix-vector multiplication (MVM) operations and large on-chip density. Despite their promises, there exist challenges in design. First, high write costs of NVMs constrain the architectural specification and pose challenges for building training accelerators. Second, the analog nature of computing introduces functional inaccuracies. In this paper, we present a design flow and necessary tools for efficient and accurate evaluation of NVM based accelerators. First, we present the higher level design flow for approaching NVM based accelerator design. Next, we present the key steps toward building an architectural simulator which can evaluate metrics such as power, performance and area as well as enable bottleneck analysis. We then present a functional simulator to evaluate algorithmic accuracy on NVM based accelerators considering the impact of various non-idealities.