This paper presents the key design techniques used in a high-speed PHY in a 3D stacking SOC using FOVEROS Through Silicon Via (TSV). This IO PHY is placed in the base die of the SOC, it needed to accommodate TSV inside the PHY to connect to the package, and it also needed to support uBump connectivity for its signal and power to support wafer level SORT testing. PHY also needed to accommodate Power/Ground TSV and uBump of the top die power delivery. The di/dt noise of the top die power/ground though this PHY posed jitter coupling issue to this PHY PLL inductor. The paper discusses how effectively TSV and uBump patterns are defined inside PHY and other layout considerations are taken care to minimize the performance impact to PHY and minimize coupling to PLL inductor from top die power di/dt and meet jitter spec.