Details
Presenter(s)
Display Name
Mustafa Oz
- Affiliation
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AffiliationUniversità degli Studi di Pavia
- Country
Abstract
A preliminary study performed before the transistor level simulations of converters with challenging specifications is presented. The target converter is a pipelined SAR ADC with 18-bit resolution that operates with a conversion rate larger than 10 MS/s. Various techniques are proposed for reducing the number of SAR conversion cycles. A calibration method for the foreground interstage gain error is also discussed.