In this work, both analogue and digital depletion mode single channel transistor circuits are presented and are simulated using an n-channel IGZO technology with VTH = -0.87V. A logic family is introduced, suppressing the need for an additional voltage level and level restoring circuitry. Furthermore, in the analogue domain, a depletion current mirror topology is presented with demonstrated small current error. Finally, the current mirror is used in the design of an OpAmp, achieving a simulated open-loop gain of 45 dB, CMRR of 58 dB, unity gain frequency of 444 kHz and a phase margin of 71 degrees.