In this paper, we present a CT C-SDM with FIR feedback to increase clock jitter robustness while preserving the anti-aliasing filtering (AAF) property of a CT modulator. The modulator also features a newly proposed DC servo loop (DSL) that extends the modulator’s dynamic range in applications with a large DC bias current. This improvement breaks the intrinsic tradeoff between dynamic range and quantization noise floor of C-SDM. Moreover, a resistive-steering DAC is proposed that allows for larger sampling frequencies than conventional resistive DACs while, at the same time, achieving lower noise floors compared to current-steering DACs. The proposed modulator architecture has been manufactured in 180nm CMOS, and consumes 64mW from a 3.3V supply. The chip’s measured peak SNR and SNDR are 77dB and 76.8 dB, respectively. The modulator can accommodate AC signal currents up to 137μApp and features an integrated noise of 6.9nArms over a 200kHz bandwidth, corresponding to a noise floor of 15pA/sqrt(Hz).