We present a fully capacitive-coupling-based SRAM CIM macro aimed at improving the energy efficiency and throughput of edge devices. The proposed architecture is built around a customized 9T1C bit-cell in charge-domain computation in 28nm technology. The proposed design supports 8192 4b × 4b MAC operations simultaneously. 4-bit input is generated by DAC, while 4b weight is achieved by a hierarchical capacity attenuator array. To minimize the expensive AD conversion, an input sparsity sensing scheme is proposed, allowing to skip redundant comparators. The proposed design achieves energy efficiency of 666 TOPS/W and throughput of 4096 GOPS.