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Video s3
    Details
    Presenter(s)
    Pramod Kumar Bharti Headshot
    Affiliation
    Affiliation
    Indian Institute of Technology, Gandhinagar
    Country
    Author(s)
    Affiliation
    Affiliation
    Indian Institute of Technology, Gandhinagar
    Display Name
    Saurabh Jain
    Affiliation
    Affiliation
    National University of Singapore
    Display Name
    Kamlesh R Pillai
    Affiliation
    Affiliation
    Intel Labs
    Affiliation
    Affiliation
    Intel Labs
    Display Name
    Gurpreet S Kalsi
    Affiliation
    Affiliation
    Intel Labs
    Display Name
    Joycee Mekie
    Affiliation
    Affiliation
    Indian Institute of Technology Gandhinagar
    Affiliation
    Affiliation
    Intel Labs
    Abstract

    This paper presents a split 6T bitcell based compute in memory subarray with variable multi-bit precision for input operands and outputs. The split wordlines of the 6T cell enable sign segregation, thus allowing arbitrary sign/magnitude multiply and accumulate operations. The energy efficiency and throughput are found out to be 95.7 TOPS/W and 546 GOPS, respectively for maximum precision of input/output. On top of that, split 6T SRAM is more resilient to write disturb than conventional 6T SRAM. Hand-written digit recognition by the proposed work showed a maximum accuracy degradation of 0.2% than that obtained from software with the same quantization.

    Slides
    • ISCAS 2022_presentation_1961.pdf (application/pdf)