Details
Presenter(s)
Display Name
Pramod Kumar Bharti
- Affiliation
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AffiliationIndian Institute of Technology, Gandhinagar
- Country
Abstract
This paper presents a split 6T bitcell based compute in memory subarray with variable multi-bit precision for input operands and outputs. The split wordlines of the 6T cell enable sign segregation, thus allowing arbitrary sign/magnitude multiply and accumulate operations. The energy efficiency and throughput are found out to be 95.7 TOPS/W and 546 GOPS, respectively for maximum precision of input/output. On top of that, split 6T SRAM is more resilient to write disturb than conventional 6T SRAM. Hand-written digit recognition by the proposed work showed a maximum accuracy degradation of 0.2% than that obtained from software with the same quantization.