Details
Presenter(s)
![Daniel García-Lesta Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/21692.jpg?h=6b698b4b&itok=INDf4tdD)
Display Name
Daniel García-Lesta
- Affiliation
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AffiliationUniversidade de Santiago de Compostela
- Country
Abstract
Background subtraction is one of the first steps in many video processing algorithms. Thus, a real-time processing with low power consumption is convenient for different applications where power hungry devices with high computational capabilities can not be deployed. This work presents the design of a 24×56 pixel proof-of-concept 0.18 μm standard CMOS vision sensor chip implementing the foreground detection algorithm Hardware Oriented Pixel Based Adaptive Segmenter (HO-PBAS) on the focal plane. Simulation results show a maximum processing speed of 2000 fps with a figure of merit of 1.3 μW/pixel at 60 fps and a pixel pitch of 47 μm in a four pixels per processing element configuration.