This paper presents a chopper instrumentation amplifier design that employs a proposed amplifier slicing technique for offset reduction. In this scheme, the core amplifier is split into multiple identical slices. During operation, the offset polarity of these slices is firstly determined by employing the second-stage of the amplifier as a static comparator. Next, by using the polarity information, the amplifier slices are regrouped to achieve statistical offset suppression. A mathematical model is developed in this paper to estimate the effectiveness of this reduction scheme. The sliced amplifier structure also enables a scalable noise and bandwidth without adding extra analog components. Simulation results show that the proposed reduction scheme achieves a > 40 dB offset suppression and a noise efficiency factor (NEF) of 2.2. The circuit is implemented in standard 0.18 μm CMOS technology for proof of concept and consumes 0.4 μA to 1 μA current from a 1.2 V supply to reach a noise level from 90 nV/√Hz to 31.8 nV/√Hz, respectively.