Approximate computing emerged as a key alternative for trading off accuracy against energy efficiency and area reduction. Adaptive filtering-based systems have been demonstrating high resiliency against hardware errors due to their intrinsic self-healing characteristic. This paper investigates the design space exploration of arithmetic approximations in a VLSI harmonic elimination (HE) hardware architecture based on Least Mean Square (LMS) adaptive filters. We evaluate the Pareto front of the area- and power versus quality curves by relaxing the arithmetic precision and by adopting both approximate multipliers (AMs) in combination with approximate adders (AAs). Our results highlight the LoBA 0 as the most efficient AM applied in the HE architecture. We combine the LoBA 0 with Copy and LOA AAs with variations in the approximation level (L). Notably, LoBA 0 and LOA with L=6 resulted in savings of 43.7% in circuit area and 45.2% in power dissipation, compared to the exact HE, which uses multiplier and adder automatically selected by the logic synthesis tool.