This paper verified a FVF with a direct-coupled auxiliary loop (DC-AL) that used a replica load technique as the reference buffer in a 12-bit 100MS/s VCM-based SAR ADC. The SAR ADC logic generated the control logic used in this technique, while the DC-AL capacitor array is small due to the design of the DC-AL control logic with an extra capacitor, technique that enhances the slew rate of the FVF without a tradeoff in its stability. The implementation of the DC-AL required less hardware overhead and all transistor-level simulations demonstrated that the DC-AL approach improved the performance of the SAR ADC with the same power consumption when compared with a conventional FVF.