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Video s3
    Details
    Presenter(s)
    Zheng Wu Headshot
    Display Name
    Zheng Wu
    Affiliation
    Affiliation
    Fudan University
    Country
    Author(s)
    Display Name
    Zheng Wu
    Affiliation
    Affiliation
    Fudan University
    Display Name
    Wuzhen Xie
    Affiliation
    Affiliation
    Fudan University
    Display Name
    Xiaoling Yi
    Affiliation
    Affiliation
    Fudan University
    Display Name
    Haitao Yang
    Affiliation
    Affiliation
    Fudan University
    Display Name
    Ruiyao Pu
    Affiliation
    Affiliation
    Fudan University
    Display Name
    Xiankui Xiong
    Affiliation
    Affiliation
    ZTE Corporation
    Display Name
    Haidong Yao
    Affiliation
    Affiliation
    ZTE Corporation
    Display Name
    Chixiao Chen
    Affiliation
    Affiliation
    Fudan University
    Display Name
    Jun Tao
    Affiliation
    Affiliation
    Fudan University
    Display Name
    Fan Yang
    Affiliation
    Affiliation
    Fudan University
    Abstract

    In this paper, we present a general RISC-V-based accelerator with a specific ping-pong buffering strategy. We propose an automated compiler based on the C backend of TVM for this accelerator. The compiler can generate high-performance low-level code using ping-pong strategy which can accelerate convolution operators at most 26%.

    Slides
    • An Automated Compiler for RISC-V Based DNN Accelerator (application/pdf)