Details
Presenter(s)
![Zheng Wu Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/18811_0.jpg?h=fbf7a813&itok=AxZRfVSz)
Display Name
Zheng Wu
- Affiliation
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AffiliationFudan University
- Country
Abstract
In this paper, we present a general RISC-V-based accelerator with a specific ping-pong buffering strategy. We propose an automated compiler based on the C backend of TVM for this accelerator. The compiler can generate high-performance low-level code using ping-pong strategy which can accelerate convolution operators at most 26%.