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![Chen Zhang Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/7309181.png?h=ff07c561&itok=3tVanjro)
- Affiliation
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AffiliationUniversity of Windsor
- Country
Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), single-electron transistors (SETs) exhibit a unique characteristic of Coulomb oscillation which can find many digital applications with area efficiency. Implementation of multiple-input XOR logic gates with SETs is such an example. This paper presents an area-efficient SET-based implementation of finite field multiplications that require a large number of XOR operations and demonstrates a great potential to explore multiplication architectures (such as Karatsuba-algorithm based multiplication) for further area savings. We show that for a 256-bit polynomial multiplier, in particular, the SET-based implementation provides up to 30% savings in terms of gate count required when compared with its traditional CMOS-based counterpart.