We investigate the performance degradation of a continuous-time pipelined (CTP) ADC due to the input load presented by the flash sub-converter. It turns out, as we show in this work, the kickback from the sub-converter degrades the linearity of the pipeline by saturating the residue amplifier. Further, that the time-varying input impedance of the flash ADC affects the alias rejection of the CTP. We propose a simple technique to alleviate these problems. The theory is borne out by simulation results from a 100,MHz bandwidth pipeline ADC designed in a 65,nm CMOS process.