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Presentations
Design and Analysis of DTC-Free ΔΣ Bang-Bang Phase-Locked Loops
Presented Date:Jul 08, 10:12am UTCPresenter(s): Zixiang Wan
A 12-Bit 2-GS/s Pipelined ADC Front-End Stage with Aperture Error Tuning and Split MDAC
Presented Date:Jul 08, 10:12am UTCPresenter(s): Peilin Yang
A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process
Presented Date:Jul 08, 10:12am UTCPresenter(s): Guruprakashkumar Peta
A Partially Binarized and Fixed Neural Network Based Calibrator for SAR-Pipelined ADCs Achieving 95.0-dB SFDR
Presented Date:Jul 08, 10:12am UTCPresenter(s): Min Chen
Wideband Digitally Controlled True Time Delay for Beamforming in a 40 nm CMOS Technology
Presented Date:Jul 08, 10:12am UTCPresenter(s): Jiachen Shen
Chairs
Chair(s)
Display Name
Taimur Rabuske
- Affiliation
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AffiliationINESC-ID
- Country
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CountryPortugal
Display Name
Zhiping Lin
- Affiliation
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AffiliationNanyang Technological University
- Country