We propose an all-standard-cell-based synthesizable SAR ADC. A differential architecture is proposed with an inverter-based resistive digital-to-analog converter (RDAC), a four-input comparator, and floating-diffusion MOSFET gate capacitors. Two prototypes have been designed in 65-nm bulk CMOS. Compared with Protype I, Prototype II has several linearity improvements of each building block. The power consumption is significantly reduced as well through improved timing control. Layout-parasitic-extraction (LPE) simulations of Prototype II suggest 35.7-dB and 47.2-dB SNDRs in 6-bit and 8-bit versions, respectively. The power consumptions are reduced to 0.91 mW and 2.52 mW, respectively.