Hyperdimensional Computing (HDC) is a computationally efficient method of performing highly-accurate classification by encoding information into very wide binary vectors with simple binary operations. In this work, we explore methods of accelerating the encoding process, demonstrated on a RISC-V processor. First, we propose a bit-serial word-parallel approach to accelerate the spatial encoder, the slowest HDC block, and demonstrate its promise with a 12.6x speedup over prior methods. Then, we describe methods to vectorize each HDC block. Implementation on a vector accelerator achieves a 12.2x speedup and 7.1x reduction in energy/prediction. Finally, we gain an additional 20% improvement in energy efficiency by finding the optimal balance between vector lanes and execution time, overall demonstrating the significant speed and energy improvements that a vector processor can provide for HDC.