We first introduce F3DC, a fast algorithm for 3D DeConv, capable of reducing the computational complexity and eliminating invalid operations related to inserted zeros. Furthermore, an efficient hardware architecture is proposed to implement the F3DC-based acceleration of 3D-GAN. Finally, we evaluate our architecture by implementing 3D-GAN model on the Xilinx VC709 platform. The experimental results demonstrate that the proposed architecture can achieve a throughput of 1700 GOPS, which surpasses prior works significantly.