Details
Presenter(s)
![Kota Shiba Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/11471.jpg?h=a0ccd589&itok=vf3DMgm3)
Display Name
Kota Shiba
- Affiliation
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AffiliationThe University of Tokyo
- Country
Abstract
A 28.8-GB/s 96-MB 3D-stacked SRAM is presented. A total of eight SRAM dies, designed in a 40-nm CMOS process, are vertically stacked and connected using an inductive coupling wireless link with a low-voltage NMOS push-pull transmitter, an inverted bit insertion scheme, a coil termination scheme, and a 12:1 SerDes. The performance of the proposed 3D-SRAM is compared with HBM DRAM and achieves more than 50% lower energy consumption. The scaling scenario of the SRAM module is discussed in light of the scaling of the inductive coupling technology and logic process.