This paper presents a 6-bit 20 GS/s 2-way time-interleaved (TI) flash analog-to-digital converter (ADC) in a 28-nm FDSOI CMOS technology. Leveraging threshold voltage control via back-gate bias in FDSOI, an automatic comparator offset calibration scheme is developed, which does not require extra transistor pairs or capacitive loads in signal path, thus avoiding comparator speed degradation. To alleviate channel mismatch-induced errors in highly interleaved structure while maintaining a reasonable power efficiency, the ADC adopts a two-way TI structure with the subADC working at 10 GS/s. To further improve the ADC power efficiency, a 1-bit voltage-domain interpolation is utilized. The proposed flash ADC achieves a SNDR of 31.2 dB at Nyquist frequency with a power consumption of 204 mW, translating into a figure-of-merit (FOM) of 344 fJ/conv.-step.