A 6b 1GS/s SAR ADC using 2b/cycle algorithm is presented. It cuts 50% of the capacitor arrays in conventional 2b/cycle architecture, which results in small input capacitance and low power consumption. A foreground offset calibration by adjusting MOSFET body capacitance and a common-mode noise reduction circuit are also proposed. The prototype ADC in 40-nm CMOS exhibits a peak SNDR of 34 dB at the conversion rate of 1GS/s with low frequency input. It consumes 4.5mW at 1.1 V supply and achieves a peak FoM of 110fJ/conversion-step. The core circuit occupies an area of 0.016 mm2.