A low power column parallel single-slope ADC with power supply noise suppression for CMOS image sensors is proposed. The ADC is composed of a dynamic bias comparator and a novel up/down double-data-rate (DDR) counter in the column. The column ADCs are divided into groups and several control signals are delayed by groups to avoid transient large current from source. A 12-bit current steering DAC with 2-dimension gradient error tolerant switching scheme is adopted as the ramp generator to improve the linearity of the ADC. The proposed techniques are experimentally verified in a prototype chip fabricated in the TSMC 180nm CMOS process. A single-column ADC consumes a total power of 63.2μW and occupies an area of 4.48μm x 310μm. The measured DNL and INL of the ADC are -0.43/+0.46 LSB and -0.84/1.95 LSB.