A fully integrated half-bridge power stage with 25V gate-drivers is designed to demonstrate a new 0.5µm SiC CMOS technology. The power stage has two 0.5Ω power FETs switching at 1MHz with 600V input and up to 1A load. The gate drivers employ a capacitive level shifter to convert the PWM control signal from the 25V control domain to the 600V power domain. The propagation delay of the gate driver is 36ns, while the slew rate of the high-side and low-side gate-drive signals are 23V/ns and 21V/ns, respectively. The switching node of the power stage has a slew rate of 31V/ns.