In this work, we present a current-controlled ring oscillator (CCRO) with an analog feedback loop that linearizes the CCRO’s signal-to-frequency tunning curve. The feedback loop is based on a frequency-dependent resistor (FDR) and a current divider. This linearization technique reduces the oscillator voltage swing, simplifying the implementation of a transconductor signal driver. We investigate the circuit parameters to optimize the trade-off between linearization and power consumption. Furthermore, an experimental 55nm CMOS chip implementing the proposed architecture has been designed and measured. The fabricated chip is intended for audio VCO-ADCs and achieves 78.15 dBA of peak SNDR with a power consumption of 153µW.