This paper presents a hybrid multiphase interleaving technique for bottom plate parasitic charge sharing and ripple reduction in SC converter (SCC). The proposed technique uses multiphase interleaving for reducing ripple and scalable parasitic charge redistribution technique for reducing bottom plate parasitic loss and incorporates them to achieve both features. The 8C8P interleaved 1/2 SCC with 3 CRS is derived using the proposed technique and implemented in the 180 nm CMOS process. Post-layout simulations of 8C8P validate that the proposed hybrid technique achieves 83% efficiency and 50% lesser ripple than the existing SPCR technique with same flying capacitance and switch conductance.