An asynchronous continuous-time level-crossing ADC for high-throughput, high-resolution applications is presented. The proposed 10-b ADC architecture comprises two stages of level-crossing ADCs, the first stage resolving for 5 MSBs and the second folded-residue stage for 5 LSBs. Compared to uniform-sampling synchronous ADCs, level-crossing ADCs (LC-ADCs) generate fewer samples for sparse signals. Unlike conventional LC-ADCs with comparators tuned for lower power consumption to acquire sparse signals, the two-tier LC-ADC is optimized for high-resolution tracking of continuous signals. Fabricated in 0.18-μm CMOS technology, chip area is 1310×125μm2. At 1.8V supply, ADC consumes 160–426μW for 1Hz to 200kHz input frequencies at full scale amplitude and achieves an energy efficiency figure-of-merit of 4.16-pJ/conv.