A 3 GS/s highly linear energy-efficient VTC has been reported in this work. The proposed VTC combines the sample and hold with constant charging process together, achieving the precise sampled step and linear ramp concurrently through charge redistribution and constant charging. It achieves 58.7 dB/-56.3 dB SFDR/THD and 144 ps output range with 0.83 mW power consumption at 3GHz clock. Implemented in 65 nm CMOS, the VTC occupies an area of 41.3 um x 34.4um.