In this paper, a 32 fs RMS jitter over-sampling phase-locked loop (OSPLL) exploiting a cross-switching phase detector (CSPD) is proposed to reduce the phase noise and RMS jitter. Firstly, The over-sampling architecture realizes the 4x$F_{REF}$ sampling frequency and a quarter of frequency divider ratio, which enables PLL to use 10 MHz loop bandwidth at 60 MHz reference frequency and achieve 32 fs RMS jitter. Secondly, CSPD can sample the highest slew rate point of quadrature reference signals to achieve high PD gain, resulting in an in-band phase noise of -136.8 dBc/Hz. Finally, the reference clock is processed into quadrature signals by RC-PPF which is composed of resistance and capacitors. RC-PPF without 1/f noise contribution effectively avoids PLL's low offset frequency phase noise.