In this work, the high SNR and energy-efficient eDRAM-CIM macro is proposed with three features: 1) High SNR voltage-based accumulation with segmented BL architecture (SBLA), resulting in 17.1 dB higher SNR, 2) canceling PVT/leakage-induced error with common-mode error canceling (CMEC) circuit, resulting in 51.4% PVT variation reduction and 51.4% refresh power reduction, 3) a ReLU-based zero-gating ADC (ZG-ADC), resulting in ADC power reduction up to 58.1%. From these features, the proposed eDRAM-CIM achieves 81.5-to-115.0 TOPS/W energy-efficiency in 4b×4b MAC with 250 MHz. The proposed macro also achieves 91.52% accuracy at the CIFAR10 dataset (ResNet-20) without accuracy drop under PVT variation.