This paper describes the design and measurementof an open-loop fractional frequency divider implementationis presented in this paper. The fractional divider consists ofa multi-modulus integer frequency divider (MMD), a sigma-delta modulator (SDM) and a pipelined phase interpolator.The fractional frequency division is achieved with the MMDand the 13-bit SDM toggling the integer division ratio. Theresulting signal is then processed by the phase interpolator whichsignificantly reduces the spurs by 22 dB and generates spectrallyclean signal with correct output frequency. The prototype isimplemented in 28-nm CMOS technology and it operates withininput frequency range of 1.9 GHz – 3.5 GHz with fractionaldivision ratio in between 2–3. As an example of the operation,with a setting of an arbitrary division ratio of 2.3164 and inputfrequency of 2.4 GHz, the output sets correctly to 1.0361 GHz with RMS jitter of 2.1 ps.