A fourth-order ∆Σ time-to-digital converter (TDC) is presented to achieve high time resolution and wide signal bandwidth. The proposed TDC is based on a 2-2 multi-stage-noise-shaping (MASH) architecture, which is built by cascading two identical single-loop second-order gated ring oscillator TDCs. To avoid common-mode errors such as supply noise and leakage current, a novel time-mode arithmetic unit with differential structure is proposed, which is expected to be the fundamental block for time-mode signal processing. Implemented in 65nm 1.2V CMOS technology, the proposed TDC achieves 336fsrms integrated noise or 1.2ps equivalent resolution within 5MHz bandwidth at 200MS/s while consuming 0.89mW.