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Video s3
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    Presenter(s)
    Yisong Kuang Headshot
    Display Name
    Yisong Kuang
    Affiliation
    Affiliation
    Peking University
    Country
    Abstract

    In this paper, we introduce a spike-based neuromorphic processor developed for efficient implementations for various neural networks including ANNs and SNNs. Based on spatio-temperal coding scheme and combinable dendrites, the chip supports input, output and weight precision between 1 bit and 8 bits, with a maximum fan-in of 72 K per neuron. The chip is implemented in 28-nm CMOS, with an energy efficiency of 0.34pJ/SOP.

    Slides
    • A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations (application/pdf)