In this paper, an all-digital delay-locked loop (ADDLL) with an adaptive phase rotator (PR) is proposed to meet the wide operating range in the LPDDR5 controllers. The conventional lattice-delay-unit (LDU)-based delay line is replaced by the PR-based digitally controlled delay line (DCDL) to achieve a wide operating range with a low jitter accumulation and low power dissipation. For the proper operation of the PR-based DCDL with high linearity, the current strength of the PR should be set to the optimum value for each operating frequency. The proposed ADDLL adaptively controls the current strength of the PR by detecting the output swing for each frequency. The proposed ADDLL is fabricated in a 28-nm CMOS technology occupying an active area of 0.0043 mm2. It operates from 266 MHz to 3750 MHz for the LPDDR5 interfaces. The measured jitterrms is 2.06 ps, and the jitterpk-pk is 13.2 ps at 3750 MHz. The proposed ADDLL consumes 4.2 mW at 3750 MHz.