This paper presents a 4kb ultra-low power static random access memory (SRAM) macro in 22nm CMOS with dynamic leakage suppression (DLS) and half-selected-free technique, typically for Internet of Things (IoT) applications requiring operation at low supply voltage. The DLS logic is used in the proposed SRAM cell to achieve ultra-low standby power, which has proved to be capable of reducing the static leakage current by 1899× compared to the conventional 6T SRAM cell. The proposed dual word line (WL) makes it possible to avoid the half-selected issues and reduces the bit line (BL) leakage by 51% compared to single WL. The SPICE simulation results done by SPECTRE simulator show that the 4kb SRAM macro designed in 22nm ultra-low leakage (ULL) CMOS technology process design kit (PDK) achieved the leakage current of 66.5 nA and the maximum operating frequency of 8.5 kHz at the minimum operating voltage of 0.2 V.