This work presents a 10.5-bit 10 MS/s SAR ADC with 1.5x input range. By pre-setting and resetting the MSB of the DAC to shift the input signal accordingly, the input range of the ADC is enhanced by a factor of 1.5. This effectively relaxes the noise requirement and thus improves the power efficiency of the ADC. The prototype implemented in 65 nm CMOS achieves a SNDR of 60.37 dB. It consumes 18.65 uW at 10 MS/s with a 0.8V supply and only occupies an area of 0.0013 mm^2. The resulting FoMW is 2.2 fJ/conversion-step.