This paper presents a 4-level pulse-amplitude modulation (PAM4) reference-less half-baud-rate clock and data recovery (CDR) incorporated with a frequency acquisition scheme to achieve 14-Gb/s data rate while extending locking range to +/-450-MHz. A combination of PAM4 data recovery units (DRUs) and integrators minimizes the clock generation and distribution overhead as well as eliminates additional front-end samplers for the edge detection. We introduce an elegant way to distill frequency information from random data without a reference clock. The proposed CDR is implemented in a 65-nm CMOS technology, consuming 30-mW that translates to 2.14 pJ/bit from a 1.2-V supply voltage, while achieving a sensitivity of 20-mV and RMS recovered clock jitter of 0.5-ps.