This paper presents a 14 - 28 G/bs reference-less Baud-rate clock and data recovery (CDR) with a stochastic phase and frequency detector (PFD). To achieve phase and frequency detection, optimum weight is determined through the histogram-based correlation of various data patterns. Many data patterns within a wide frequency range are utilized to demonstrate robust operation. The reference-less Baud-rate CDR is implemented utilizing data samples and phase error samples obtained from the integrator. The proposed CDR is designed to achieve a data rate of up to 28 Gb/s employing a continuous-time linear equalizer (CTLE) under a 4.7-dB data loss channel at Nyquist frequency. Fabricated in 28-nm CMOS technology, the proposed CDR achieves a bit error rate (BER) < 10-12 and an energy efficiency of 1.06 pJ/b.