This paper presents implementation of a CMOS image sensor with a 65nm CMOS process. The pixel array consists of 13Mp in 1.12um pixel pitch. The fabricated sensor uses 10-bit column-parallel single slope analog-to-digital converters (ADCs) based on a low-power counter architecture. Furthermore, to avoid test over-kills, a low-power built-in self-test (BIST) is proposed. The proposed image sensor achieves a frame rate of 120 frames/s, 2e-rms temporal random noise, dynamic range is 65.2dB, 0.18% peak integral non-linearity and 0.26LSB peak differential non-linearity. Total chip power consumption is only 99.7mW at 30frames/s movie mode.