This paper presents a 12-bit Current-Steering digital-to-analog converter (DAC) with a multi-segment architecture implemented in GSMC 1P-5M 0.11-um CMOS process. To reach high linearity and large-swing output voltage, a complementary switch array and a current source array with cascode devices are employed. Digital latches and cross-point adjustment circuits for switch control signal are introduced to suppress glitches. In order to facilitate the DAC to use as a stand alone module, a high-speed deserializer is integrated on the chip and an internal bandgap reference has also been implemented. The simulation results show that under the 1.5/3.3 V power supply voltage, DNL is below ±0.08 LSB and INL is below ±0.35 LSB. When the sampling clock of DAC is 50 MS/s and 100 MS/s, the spurious free dynamic range (SFDR) of DAC in the whole Nyquist domain is greater than 72 dB and 66 dB respectively, the effective number of bits (ENOB) of DAC is all greater than 11 bits.