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Presenter(s)
![Siyu Tan Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/12621.jpg?h=8f391919&itok=Z1axbLaE)
Display Name
Siyu Tan
- Affiliation
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AffiliationLund University
- Country
Abstract
This paper presents a 10-bit SAR ADC with a sampling rate of 200 MS/s. To reduce area and power consumption, the ADC adopts a split-capacitor DAC, where the gain error is estimated and subsequently removed by means of a PRBS signal injected into the DAC and detected at the ADC output. The ADC has been designed and fabricated in a 22nm FD-SOI CMOS process, and achieves an SNDR of 48.7 dB and an SFDR of 66.7 dB for input frequencies up to the sampling frequency, with a power consumption of 4.3mW and an FoM of 152 dB.