This paper presents a single-channel two-stage pipelined-SAR ADC with ping-pong switched half of capacitordigital-to-analog-converter (CDAC) moving the residue amplification into 2nd stage to lighten the timing burden of the 1st stage. Besides, a dynamic open-loop residue amplifier (RA) is employed to improve the energy efficiency and amplification speed. In order to enhance the ADC robustness, the gain variation under the supply and temperature drift are suppressed through the supply-and-temperature compensation bias.