This work examines a combination of design optimizations for efficient all-digital skew mismatch correction in time interleaved ADCs, enabling delay tuning ranges up to 0.12 of sampling period at 10-bit ADC resolution and providing usable bandwidth of beyond 0.9 Nyquist band while operating at a clock rate of a single ADC channel. The proposed digital structure is suitable for on-chip implementation in highly parallelized high-speed converter designs.