A 0.13mJ/prediction 68.6% accuracy CIFAR-100 single-chip wired-logic AI processor is developed with 16nm FPGA. The energy efficiency is improved by 238 times compared with state-of-the-art FPGA-based processor by eliminating the DRAM/BRAM access. A technical challenge of the conventional wired-logic processor is a large number of hardware resources. To implement a large CNN into a single FPGA chip, two techniques are used: (1) a sparse neural network which is called non-linear neural network (NNN) to reduce the network size by 80%, and (2) a newly developed raster-scan-based wired-logic architecture to reduce hardware size by a factor of 5.4.