Details
Presenter(s)
Display Name
Yandong Luo
- Affiliation
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AffiliationGeorgia Institute of Technology
- Country
Abstract
Three techniques are proposed to mitigate inference accuracy degradation due to the non-ideal device property of STT-MRAM: 2T-2MTJ bit-cell, redundancy for MSB weights and hybrid-layer mapping scheme. Benchmarking results show that inference accuracy can be maintained at >87.5% for CIFAR10, with minimal 8% energy and 4% chip area overhead.