Polar Codes are considered as channel standards for 5G communications. Successive Cancellation (SC) decoder is the most popular and the simplest among all Polar code decoders. Various designs, including split-g node, and two-phase semi-parallel architectures, were proposed in the past to reduce the hardware of SC decoders. However, no architecture explored the impact of variable quantization on the hardware resources while maintaining decoding performance. We propose an efficient hardware design of SC decoder based on variable quantization. Synthesis results show that our FPGA implementation provides up to 63% saving in hardware resources as compared to conventional architecture. Similarly, our ASIC implementation resulted in a min of 2.9× and 1.86× savings in gate count and power consumption, respectively. The total energy analysis indicates that our proposed decoder results in lesser energy for devices operating in the range of 50 meters which is an ideal range for many IoT-based technologies including Bluetooth, BLE, Zigbee, etc.